/*
 * Copyright (c) 2004-2006 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Gou Pengfei
 * Date:    April. 2011
 */

#ifndef __CPU_EDGE_TWOSTAGE_FRAMEWORK_HH__
#define __CPU_EDGE_TWOSTAGE_FRAMEWORK_HH__

#include <vector>
#include <deque>

#include "base/types.hh"
#include "cpu/edge/sat_counter.hh"
#include "cpu/edge/pred/base_type_predictor.hh"
#include "cpu/edge/pred/base_binary_predictor.hh"
#include "config/the_isa.hh"
#include "arch/isa_traits.hh"
#include "params/DerivEdgeCPU.hh"

/**
 * A class to implement the framework of two-stage predictor, in
 * which the first stage is a binary predictor to distinguish between
 * sequential targets and others, while the second stage is a branch
 * type predictor to distinguish between the other targets.
 * */
template<class Impl>
class TwostageFramework
{
  public:
    typedef TheISA::BlockID BlockID;
    typedef TheISA::BTypeID BTypeID;
    typedef typename Impl::EdgeBlockPtr BlockPtr;

    enum PredictorMode {
        InvalidMode,
        Normal,
        PerfectSequential
    };

    TwostageFramework(DerivEdgeCPUParams *params);

    ~TwostageFramework();

    void reset();	

    /**
     * Looks up the given block address in the branch predictor and returns
     * an type ID of the block. Add block pointer to arguments for perfect
     * sequential predictor.
     */
    TheISA::BTypeID lookup(BlockPtr & block, BlockID block_id,
            BlockID oldest_block_id, Addr block_pc, int addr_space_id,
            ThreadID tid);

    /**
     * Updates the branch predictor with the actual result of a branch.
     */
    void update(BlockID block_id, Addr block_pc, int addr_space_id,
                BTypeID actual_type_id, ThreadID tid, bool seq_mispredicted);

    /**
     * Restores the global branch history on a squash.
     */
    void squash(BlockID block_id, Addr block_pc, BTypeID type_id,
            int addr_space_id, ThreadID tid, bool seq_mispredicted);

    /**
     * Restores the global branch history on a squash.
     */
    void squash(BlockID block_id, ThreadID tid);

    uint64_t lookupGetIndex(Addr &block_PC, ThreadID tid);

    uint64_t updateGetIndex(BlockID block_id, Addr &block_PC, ThreadID tid);

    void regStats();

    uint64_t getPathHistory(ThreadID tid)
    { 
        assert(stage1 != NULL);
        return stage1->getPathHistory(tid); 
    }

    uint64_t getPathHistory(BlockID block_id, ThreadID tid)
    { 
        assert(stage1 != NULL);
        return stage1->getPathHistory(block_id, tid); 
    }

    uint64_t getGlobalHistory(ThreadID tid) 
    {
        assert(stage1 != NULL);
        return stage1->getGlobalHistory(tid); 
    }

    uint64_t getGlobalHistory(BlockID block_id, ThreadID tid)
    {
        assert(stage1 != NULL);
        return stage1->getGlobalHistory(block_id, tid);
    }

    bool isPerfectSeq() { return (predictorMode == PerfectSequential); }

  private:

    PredictorMode predictorMode;

    BaseBinaryPredictor<Impl> * stage1;

    BaseTypePredictor<Impl> * stage2;

    void initVars();

};

#endif // __CPU_EDGE_TWOSTAGE_FRAMEWORK_HH__
